In an RF circuit for a cellular or mobile phone or the like, in recent years, an analog circuit is also manufactured according to a microfabrication process, and a circuit provided with a digital circuit and an analog circuit mounted in a mixed manner (which is called “mixed signal circuit”) has been used. In such a mixed signal circuit, a depletion-mode MOS transistor used in an analog circuit such as a regulator section is required in addition to an enhancement-mode MOS transistor configuring a digital circuit in a logical section. Regarding MOS transistors of an N type, for example, a threshold voltage of an enhancement-mode N-type MOS transistor is a positive value, while a depletion-mode N-type MOS transistor is a MOS transistor having a threshold voltage of a negative value. Regarding absolute values of threshold voltages of the enhancement-mode and depletion-mode MOS transistors used in the mixed signal circuit, generally, the absolute value of the latter is often smaller than that of the former. Since electric characteristics of a MOS transistor used in the analog circuit influence the circuit operation, it is required to arrange a plurality of MOS transistors with different threshold voltages within the same or one semiconductor substrate with a high precision.
Incidentally, when magnitudes of threshold voltages are compared with each other in the present specification, the comparison is performed based upon absolute values of the threshold voltages. That is, threshold voltages of an enhancement-mode N-type MOS transistor and a depletion-mode P-type MOS transistor take positive values while threshold voltages of a depletion-mode N-type MOS transistor and an enhancement-mode P-type MOS transistor take negative values, but magnitudes of their absolute values of the threshold values are compared with each other when magnitudes of the threshold voltages are compared. The term “MOS transistor” is also used to mean an ordinary insulated gate field effect transistor.
After the inventors of the present invention had completed the present invention, they conducted a prior art search from the standpoint of prior art referring to a relationship between halo implantation and a threshold voltage of a MOS transistor, so that they found Japanese Patent Application Laid-Open Publication No. 2000-150885 (Patent Document 1) and Japanese Patent Application Laid-Open Publication No. 2001-7330 (Patent Document 2).
Patent Document 1 discloses that, based on a consideration that impurities implanted into a channel region diffused in a thermal treatment step are the cause of a variation in the threshold voltage of a transistor, the variation in the threshold voltage of the transistor is eliminated by aggressively controlling an implantation amount of the impurities implanted into a halo layer performed after a thermal treatment step.
Patent Document 2 discloses that, since an impurity concentration on a source side of a transistor strongly influences a threshold voltage of the transistor while an impurity concentration on a drain side of the transistor strongly influences a short-channel effect, different impurity concentrations are used in halo implantation regions on source and drain sides in order to improve both of the low threshold voltage (a halo layer acts so as to raise the threshold voltage) and the short-channel effect resistance.